QuickLogic and eTopus Announce Disaggregated and Flexible eFPGA Chiplet Model | New

– Target advanced and high-performance applications

– Available initially as Configurable IP and later as Known Good Die Chiplets

SAN JOSE, CA., June 16, 2022 /PRNewswire/ — QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low-power multi-core voice-enabled SoCs, embedded FPGA IP solutions and endpoint artificial intelligence, and eTopus, a leader in high-speed solutions , low latency, low powerconnectivity IP, today announced the industry’s first eFPGA-enabled disaggregated chip model solution. Based on QuickLogic’s Australis™ eFPGA IP generator and eTopus’ industry-leading chip interfaces, the model offers unprecedented design flexibility and bandwidth for high-performance applications.

Unlike discrete FPGAs with predetermined resources of FPGA LUTs, RAM, and I/O, the eFPGA-compatible disaggregated chiplet model will initially be available as configurable IPs, and eventually as Known Good Die (KGD) chiplets . Each model will be designed with native support for emerging industry chip interfaces, including Bunch of Wires (BOW) and UCIe standards, enabling seamless integration with a customer’s own devices. This approach allows customers to size the solution according to their needs while being compatible with emerging chip standards.

The initial model will use 6nm process technology to balance performance and cost. eFPGA LUT counts will begin to 200K with additional functionality available in RAM and Digital Signal Processing (DSP) blocks. Surrounding the eFPGA core will be up to 384 Die2Die links developed by eTopus. Each link can operate at 0.5/4/8/16G and is x64 block organized to efficiently transport Ethernet, PCIe, AI/ML and compute traffic.

“Leveraging our proven Australis eFPGA IP compiler, we are now able to produce standard eFPGA-compatible chip designs as well as more application or customer optimized chip designs within months,” said Brian Faith, president and CEO of QuickLogic. “This positions our solution to serve a wide range of high-performance, low-power applications, allowing our customers to not only size the eFPGA to suit their needs, but also to focus on what differentiates their products in the market. .

eTopus is developing an extended version of the BOW interface as well as the new UCIe standard for low-power, low-latency die-to-die connectivity. It also plans to develop add-on I/O chips that will be available as IP and Known Good Die (KGD) with partners.

“We are excited to support QuickLogic’s disaggregated eFPGA chip model solution,” said Harry Chan, CEO of eTopus. “For 6nm, eTopus has existing 112G SerDes for Ethernet IP and PCIe Gen 5 and 6 PHYs and controllers that are available for design now. Our high-speed mixed-signal technology will provide the glue to connect QuickLogic’s eFPGA chip designs to other I/O and SOC chiplets via our die-to-die technology, which offers industry-leading

Availablity

Availability of the chiplet model is expected in the first half of 2023. Interested customers can contact QuickLogic at [email protected] or eTopus at [email protected]

About eTopus Technology Inc.

eTopus is the technology leader in high-performance, DSP-based, mixed-signal, ultra-fast semiconductor interconnect solutions. Our ultra-fast SerDes IP is being adopted by global Tier 1 players for use in networking, storage, 5G and AI applications. eTopus is a VC-backed startup headquartered in Silicon Valley, where our innovations and advanced architectures are developed. Our investors include SK Telecom, HK-X, venture capitalists and cross-border funds. For more information, visit www.etopus.com.

About QuickLogic

QuickLogic Corporation (NASDAQ: QUIK) is a fabless semiconductor company that develops multi-core, low-power semiconductor platforms and intellectual property (IP) for artificial intelligence (AI), voice and sensors. Solutions include embedded IP FPGA (eFPGA) for hardware acceleration and preprocessing, and heterogeneous multi-core SoCs that integrate the eFPGA with other processors and peripherals. The analytics toolkit of our recently acquired wholly-owned subsidiary, SensiML Corporation, completes the end-to-end solution with accurate sensor algorithms using AI technology. The full range of eFPGA platforms, software tools, and IP enables the practical and efficient adoption of AI, voice, and sensor processing on mobile, wearable, audible, consumer, industrial, peripheral and terminal. For more information, visit www.quicklogic.com and https://www.quicklogic.com/blog/.

The QuickLogic logo and QuickLogic are registered trademarks of QuickLogic Corporation. All other trademarks or registered trademarks are the property of their respective owners and should be treated as such.

View original content for multimedia download: https://www.prnewswire.com/news-releases/quicklogic-and-etopus-announce-disaggregated-flexible-efpga-chiplet-template-301569363.html

SOURCEQuickLogic Corporation